1. Field of the Invention
The present invention is related to a System in Package (SIP) integrated circuit, and more particularly, to a SIP integrated circuit which self-generates an input reference voltage.
2. Description of the Prior Art
As the development of the integrated circuit process advances, the capacity and the operational speed of the memory progress exponentially, for which various memory specifications are introduced successively. Double Data Rate (DDR) standard is a well known specification, and the relative DDR standard (such as the DDR standard of the JESD79 series formulated by the JEDEC association) is recited to assist explaining the present invention. In DDR standard, it is denoted that all inputs of DDR standard are compatible with the SSTL—2 standard, which is another standard developed by the JEDEC association. The SSTL—2 standard is also recited to assist the explanation of the present invention.
The purpose of the SSTL—2 standard is to regulate the 2.5 volt (V) interface standard of the digital integrated circuit, as shown in FIG. 1. FIG. 1 is a diagram illustrating an embodiment of a circuitry according to the SSTL—2 standard, wherein the output buffer 110 of the first digital integrated circuit 10 generates an output signal VOUT, and the input circuit 210 of the second digital integrated circuit 20 receives the output signal VOUT and then generates an input signal for the second digital integrated circuit 20 to make use of, according to an input reference voltage VREF. For the output signal VOUT to maintain a decent signal waveform (i.e. decent signal integrity) during transmission, a serial resistor RS is coupled between the first digital integrated circuit 10 and the second digital integrated circuit 20, and one end of another terminal resistor RT is coupled between the serial resistor RS and the second digital integrated circuit 20, wherein the other end of the terminal resistor RT is coupled to a terminal voltage VTT. In this embodiment, the serial resistor RS and the terminal resistor RT are realized with resistors of 25 Ohms and 50 Ohms, respectively. Generally, the input circuit 210 is of a comparator, in which one input end receives the input reference voltage VREF and the other input end receives the output signal VOUT generated from the first digital integrated circuit 10. For the first digital integrated circuit 10 and the second digital integrated circuit 20 to utilize the similar input reference voltage VREF, the input reference voltage VREF required by the input circuit 210 is generally generated directly from the first digital integrated circuit 10.
In practical applications, the DDR memory chip is often composed into the system in package with another logic circuit chip, as shown in FIG. 2A and FIG. 2B. FIG. 2A is a diagram illustrating a stack packaging technique utilized in the SIP, wherein the DDR memory chip 310 is disposed onto the logic circuit chip 320 and the stack chip set (i.e. DDR memory chip 310 plus the logic circuit chip 320) is then disposed onto the base board 330. The relative input/output (I/O) pins of the DDR memory chip 310, the logic circuit chip 320 and the base board are subsequently wire bonded. FIG. 2B is a diagram illustrating another structure of SIP, wherein the DDR memory chip 310 and the logic circuit chip 320 are disposed respectively onto the base board 330, the relative input/output (I/O) pins of the DDR memory chip 310 and the logic circuit chip 320 are then wire bonded to the external connection pins of the base board 330. However, the integrated circuits of such SIP mentioned above are somewhat flawed; for instances, there are times when the selected logic circuit chip 320 is unable to provide the input reference voltage VREF for the DDR memory chip 310 to use; or the output pin of the logic circuit chip 320 providing the input reference voltage VREF is not located on the same side as the input pin of the DDR memory chip 310 receiving the input reference voltage VREF, increasing the difficulty/complexity of the wiring bonding.